1. Field of Invention
The present invention relates to a method of manufacturing a semiconductor device. More particularly, the present invention relates to a method of manufacturing a spacer.
2. Description of Related Art
When the integration of the integrated circuit is getting increased, the size of the semiconductor device is decreased. Therefore, the length of the channel in the substrate under the gate structure is also decreased. However, when the length of the channel is shrinking into a certain level, the problems caused by relatively short channel length happen. That is so-called Short Channel Effect. Currently, the Lightly-Doped-Drain (LDD) design is the most common way to solve the Short Channel Effect. In this kind of design, a lightly doped source/drain region is further formed in the substrate closely adjacent to the channel between the original source/drain region of the metal oxide semiconductor (MOS).
Under the LDD design, a spacer is required to form on the sidewall of the gate structure. Conventionally, the spacer is made of silicon oxide. Nevertheless, the material of silicon oxide possesses the characteristic of absorbing moisture. Recently, an oxide-nitride-oxide material is used to form the spacer. FIG. 1 is a cross-sectional view showing a gate structure having an oxide-nitride-oxide spacer. As shown in FIG. 1, a gate structure 102 having a spacer structure 104 is located on a substrate 100. The gate structure 102 comprises a gate dielectric layer 102a and a gate electrode 102b. The spacer structure 104 comprises a bottom oxide spacer 106, a middle L-shape nitride spacer 108 and an upper oxide spacer 110. Because of the wet etching process for removing a portion of the bottom oxide layer until the bottom oxide spacer 106 is formed, an under-cut phenomenon 112 happens on the bottom oxide spacer 106 under the middle L-shape nitride spacer 108. As a result, it is not easy to control the actual lateral length of the MOS. Therefore, the margin of the later formed source/drain region (not shown) in the substrate 100 by performing an ion implantation process cannot be well controlled and the uncertain margin of the source/drain region leads to unexpected electrical performance of the semiconductor device. Further, the reliability of the semiconductor device is decreased as well.